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1 features ? standard-voltage operation ? 2.7 (v cc = 2.7v to 5.5v) low-power devices (i sb = 6 a @ 5.5v) available internally organized 4096 x 8, 8192 x 8 two-wire serial interface schmitt trigger, filtered inputs for noise suppression bidirectional data transfer protocol 400 khz (2.7v) clock rate for at24c32a/64a write protect pin for ha rdware data protection 32-byte page write mode (partial page writes allowed) self-timed write cycle (5 ms max) high reliability ? endurance: 1 million write cycles ? data retention: 100 years lead-free/halogen-free devices available 8-lead jedec pdip, 8-lead jedec soic and 8-lead tssop packages description the at24c32a/64a provides 32,768/65,536 bits of serial electrically erasable and programmable read only memory (eeprom) organized as 4096/8192 words of 8 bits each. the device?s cascadable feature allows up to 8 devices to share a common two- wire bus. the device is optimized for use in many industrial and commercial applica- tions where low power and low voltage operation are essential. the at24c32a/64a is available in space saving 8-lead jede c pdip, 8-lead jedec soic and 8-lead tssop packages and is accessed via a 2-wire serial interface. in addition, the entire family is available in 2.7v (2.7v to 5.5v). table 1. pin configuration pin name function a0 ? a2 address inputs sda serial data scl serial clock input wp write protect two-wire automotive serial eeprom 32k (4096 x 8) 64k (8192 x 8) at24c32a at24c64a 5120a?seepr?10/05 8-lead pdip 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda 8-lead soic 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda 8-lead tssop 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda
2 at24c32a/64a 5120a?seepr?10/05 figure 1. block diagram absolute maximum ratings* operating temperature..................................?55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .....................................?65 c to +150 c voltage on any pin with respect to ground .................................... ?1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma
3 at24c32a/64a 5120a?seepr?10/05 pin description serial clock (scl): the scl input is used to positive edge clock data into each eeprom device and negat ive edge clock data out of each device. serial data (sda): the sda pin is bidirectional for serial data transfer. this pin is open-drain driven and may be wire-ored with any number of other open-drain or open collector devices. device/addresses (a2, a1, a0): the a2, a1 and a0 pins are device address inputs that are hardwired or left not connected for hardware compatibility with other at24cxx devices. when the pins are hardwired, as many as eight 32k/64k devices may be addressed on a single bus system (device addressing is disc ussed in detail under the device addressing section). if the pins are left floating, the a2, a1 and a0 pins will be internally pulled down to gnd if the capacitive coupling to the circuit board v cc plane is <3 pf. if coupling is >3 pf, atmel recomm ends connecting the address pins to gnd. write protect (wp): the write protect input, when connected to gnd, allows nor- mal write operations. when wp is connected high to v cc , all write operations to the memory are inhibited. if the pin is left floating, the wp pin will be internally pulled down to gnd if the capacitive coupling to the circuit board v cc plane is <3 pf. if coupling is >3 pf, atmel recommends connecting the pin to gnd. switching wp to v cc prior to a write operation creates a software write protect function. memory organization at24c32a/64a, 32k/64k serial eeprom: the 32k/64k is internally organized as 128/256 pages of 32 bytes each. random word addressing requires a 12/13-bit data word address.
4 at24c32a/64a 5120a?seepr?10/05 note: 1. this parameter is characterized and is not 100% tested. note: 1. v il min and v ih max are reference only and are not tested. table 2. pin capacitance (1) applicable over recommended operating range from t a = 25 c, f = 1.0 mhz, v cc = +1.8v symbol test condition max units conditions c i/o input/output capacitance (sda) 8 pf v i/o = 0v c in input capacitance (a 0 , a 1 , a 2 , scl) 6 pf v in = 0v table 3. dc characteristics applicable over recommended operating range from: t a = ? 40 c to +125 c,v cc = +2.7v to +5.5v (unless otherwise noted) symbol parameter test condition min typ max units v cc3 supply voltage 2.7 5.5 v i cc1 supply current v cc = 5.0v read at 400 khz 0.4 1.0 ma i cc2 supply current v cc = 5.0v write at 400 khz 2.0 3.0 ma i sb3 standby current (2.7v option) v cc = 2.7v v in = v cc or v ss 2.0 a i li input leakage current v in = v cc or v ss 0.10 3.0 a i lo output leakage current v out = v cc or v ss 0.05 3.0 a v il (1) input low level ?0.6 v cc x 0.3 v v ih (1) input high level v cc x 0.7 v cc + 0.5 v v ol2 output low level v cc = 3.0v i ol = 2.1 ma 0.4 v v ol1 output low level v cc = 1.8v i ol = 0.15 ma 0.2 v
5 at24c32a/64a 5120a?seepr?10/05 notes: 1. this parameter is characterized and is not 100% tested. table 4. ac characteristics applicable over recommended operating range from t a = ? 40 c to +125 c, v cc = +2.7v to +5.5v, cl = 1 ttl gate and 100 pf (unless otherwise noted) symbol parameter at24c32a at24c64a units 2.7v ? 5.0v 2.7v ? 5.0v min max min max f scl clock frequency, scl 400 400 khz t low clock pulse width low 1.3 1.2 s t high clock pulse width high 0.6 0.6 s t i noise suppression time (1) 50 50 ns t aa clock low to data out valid 0.1 0.9 0.1 0.9 s t buf time the bus must be free before a new transmission can start (1) 1.3 1.2 s t hd.sta start hold time 0.6 0.6 s t su.sta start set-up time 0.6 0.6 s t hd.dat data in hold time 0 0 s t su.dat data in set-up time 100 100 ns t r (1) inputs rise time 0.3 0.3 s t f (1) inputs fall time 300 300 ns t su.sto stop set-up time 0.6 0.6 s t dh data out hold time 50 50 ns t wr write cycle time 5ms 5ms ms endurance (1) 5.0v, 25 c, page mode 1m 1m write cycles
6 at24c32a/64a 5120a?seepr?10/05 device operation clock and data transitions: the sda pin is normally pulled high with an exter- nal device. data on the sda pin may change only during scl low time periods (refer to data validity timing diagram). data changes during scl high periods will indicate a start or stop condition as defined below. start condition: a high-to-low transition of sda with scl high is a start condition which must precede any other command (see figure 5 on page 8). stop condition: a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the eeprom in a standby power mode (see figure 5 on page 8). acknowledge: all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eeprom sends a zero during the ninth clock cycle to acknowledge that it has received each word. standby mode: the at24c32a/64a features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the stop bit and the completion of any internal operations. memory reset: after an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: (a) clock up to 9 cycles, (b) look for sda high in each cycle while scl is high and then (c) create a start condition as sda is high.
7 at24c32a/64a 5120a?seepr?10/05 figure 2. bus timing scl: serial clock, sda: serial data i/o figure 3. write cycle timing scl: serial clock, sda: serial data i/o note: 1. the write cycle time t wr is the time from a valid stop condition of a write s equence to the end of the internal clear/write cycle. figure 4. data validity t wr (1) stop condition start condition wordn ack 8th bit scl sda
8 at24c32a/64a 5120a?seepr?10/05 figure 5. start and stop definition figure 6. output acknowledge
9 at24c32a/64a 5120a?seepr?10/05 device addressing the 32k/64k eeprom requires an 8-bit device address word followi ng a start condition to enable the chip for a read or write operation (see figure 7 on page 11). the device address word consists of a mandatory one, ze ro sequence for the first four most signifi- cant bits as shown. this is common to all 2-wire eeprom devices. the 32k/64k uses the three device address bits a2, a1, a0 to allow as many as eight devices on the same bus. these bits must compare to their corresponding hardwired input pins. the a2, a1, and a0 pins use an in ternal proprietary circuit that biases them to a logic low condition if th e pins are allowed to float. the eighth bit of the device address is the read/write operation select bit. a read opera- tion is initiated if this bit is high and a writ e operation is initiate d if this bit is low. upon a compare of the device address, the eeprom will output a ze ro. if a compare is not made, the devi ce will return to standby state. noise protection: special internal circuitry placed on the sda and scl pins pre- vent small noise spikes from activating the device. data security: the at24c32a/64a has a hardware data protection scheme that allows the user to write protect the entire memory when the wp pin is at v cc . write operations byte write: a write operation requires two 8-bit data word addresses following the device address word and acknowledgment. upon receipt of this address, the eeprom will again respond with a zero and then cloc k in the first 8-bit data word. following receipt of the 8-bit data word, the ee prom will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condi- tion. at this time the eeprom enter s an internally-timed write cycle, t wr , to the nonvolatile memory. a ll inputs are disabled during th is write cycle and the eeprom will not respond until the write is complete (see figure 8 on page 11). page write: the 32k/64k eeprom is capab le of 32-byte page writes. a page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. instead, after the eeprom acknowledges receipt of the first data word, the microcontroller can transmit up to 31 more data words. the eeprom will respond with a zero after each data word received. the microcontroller must terminate the page write sequence with a stop condition (see figure 9 on page 11). the data word address lower five bits are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. if more than 32 data words are transmitted to the eeprom, the data wo rd address will ?roll over? and previous data will be overwritten. acknowledge polling: once the internally-timed write cycle has started and the eeprom inputs are disabl ed, acknowledge polling can be in itiated. this involves send- ing a start condition followed by the device address word. the read/write bit is representative of the operation desired. only if the internal write cycle has completed will the eeprom respond with a ze ro, allowing the read or wr ite sequence to continue.
10 at24c32a/64a 5120a?seepr?10/05 read operations read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. there are three read operations: current address read, random address read and sequential read. current address read: the internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. the address ?roll over? during read is from the last byte of the last memory page, to the first byte of the first page. the address ?roll over? during write is from the last byte of the cur- rent page to the first byte of the same page. once the device address with the read/write select bit set to one is clocked in and acknowledged by the eeprom, the current addr ess data word is serially clocked out. the microcontroller does not respond with an input zero but does generate a following stop condition (see figure 10 on page 11). random read: a random read requires a ?dummy? byte write sequence to load in the data word address. once the device address word and data word address are clocked in and acknowledged by the eeprom, the microcontroller must generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. the eeprom acknowledges the device address and serially clocks out the data word. the microcontroller does not respond with a zero but does generate a following stop condition (see figure 11 on page 12). sequential read: sequential reads are initiated by either a current address read or a random address read. after the microcontroller receives a data word, it responds with an acknowledge. as long as the eeprom re ceives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. when the memory address limit is reached, the data word address will ?roll over? and the sequen- tial read will continue. th e sequential read operatio n is terminated when the microcontroller does not respond with a ze ro but does generate a following stop condi- tion (see figure 12 on page 12).
11 at24c32a/64a 5120a?seepr?10/05 figure 7. device address figure 8. byte write figure 9. page write notes: 1. * = don?t care bits 2. ? = don?t care bits for the 32k figure 10. current address read
12 at24c32a/64a 5120a?seepr?10/05 figure 11. random read note: 1. * = don?t care bits figure 12. sequential read
13 at24c32a/64a 5120a?seepr?10/05 notes: 1. for 2.7v devices used in the 4.5v to 5.5v range, please refer to performance values in the ac and dc characteristics tables. 2. ?q? designates green package and rohs compliant. at24c32a ordering information (1) ordering code package operation range at24c32a-10pe-2.7 at24c32an-10se-2.7 at24c32a-10te-2.7 8p3 8s1 8a2 automotive (?40 c to 125 c) at24c32a-10pq-2.7 (2) at24c32an-10sq-2.7 (2) at24c32a-10tq-2.7 (2) 8p3 8s1 8a2 lead-free/halogen-free/ automotive (?40 c to 125 c) package type 8p3 8-lead, 0.300" wide, plastic dual in-line package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) 8a2 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) options ? 2.7 low voltage (2.7v to 5.5v)
14 at24c32a/64a 5120a?seepr?10/05 notes: 1. for 2.7v devices used in the 4.5v to 5.5v range, please refer to performance values in the ac and dc characteristics tables. 2. ?q? designates green package and rohs compliant. at24c64a ordering information (1) ordering code package operation range at24c64a-10pe-2.7 at24c64an-10se-2.7 at24c64a-10te-2.7 8p3 8s1 8a2 automotive (?40 c to 125 c) at24c64a-10pq-2.7 (2) at24c64an-10sq-2.7 (2) at24c64a-10tq-2.7 (2) 8p3 8s1 8a2 lead-free/halogen-free/ automotive (?40 c to 125 c) package type 8p3 8-lead, 0.300" wide, plastic dual in-line package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) 8a2 8-lead, 4.4mm body, plastic thin shrink small outline package (tssop) options ? 2.7 low voltage (2.7v to 5.5v)
15 at24c32a/64a 5120a?seepr?10/05 package drawings 8p3 ? pdip 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 8 p 3 , 8 -le a d, 0. 3 00" wide body, pl as tic d ua l in-line p a ck a ge (pdip) 01/09/02 8 p 3 b note s : 1. thi s dr a wing i s for gener a l inform a tion only; refer to jedec dr a wing m s -001, v a ri a tion ba, for a ddition a l inform a tion. 2. dimen s ion s a a nd l a re me asu red with the p a ck a ge s e a ted in jedec s e a ting pl a ne g au ge g s - 3 . 3 . d, d1 a nd e1 dimen s ion s do not incl u de mold fl as h or protr us ion s . mold fl as h or protr us ion s s h a ll not exceed 0.010 inch. 4. e a nd ea me asu red with the le a d s con s tr a ined to b e perpendic u l a r to d a t u m. 5. pointed or ro u nded le a d tip s a re preferred to e as e in s ertion. 6. b 2 a nd b3 m a xim u m dimen s ion s do not incl u de d a m ba r protr us ion s . d a m ba r protr us ion s s h a ll not exceed 0.010 (0.25 mm). common dimen s ion s (unit of me asu re = inche s ) s ymbol min nom max note d d1 e e1 e l b 2 b a2 a 1 n ea c b3 4 plc s a ? ? 0.210 2 a2 0.115 0.1 3 0 0.195 b 0.014 0.01 8 0.022 5 b 2 0.045 0.060 0.070 6 b3 0.0 3 0 0.0 3 9 0.045 6 c 0.00 8 0.010 0.014 d 0. 3 55 0. 3 65 0.400 3 d1 0.005 ? ? 3 e 0. 3 00 0. 3 10 0. 3 25 4 e1 0.240 0.250 0.2 8 0 3 e 0.100 b s c ea 0. 3 00 b s c 4 l 0.115 0.1 3 0 0.150 2 top view s ide view end view
16 at24c32a/64a 5120a?seepr?10/05 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. note: 3/17/05 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 c common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 0? ? 8? ? ? e e 1 1 n n top view top view c c e1 e1 end view a a b b l l a1 a1 e e d d side view side view
17 at24c32a/64a 5120a?seepr?10/05 8a2 ? tssop 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 5/ 3 0/02 common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note d 2.90 3 .00 3 .10 2, 5 e 6.40 b s c e1 4. 3 0 4.40 4.50 3 , 5 a ? ? 1.20 a2 0. 8 0 1.00 1.05 b 0.19 ? 0. 3 0 4 e 0.65 b s c l 0.45 0.60 0.75 l1 1.00 ref 8 a2 , 8 -le a d, 4.4 mm body, pl as tic thin s hrink s m a ll o u tline p a ck a ge (t ss op) note s : 1. thi s dr a wing i s for gener a l inform a tion only. refer to jedec dr a wing mo-15 3 , v a ri a tion aa, for proper dimen s ion s , toler a nce s , d a t u m s , etc. 2. dimen s ion d doe s not incl u de mold fl as h, protr us ion s or g a te bu rr s . mold fl as h, protr us ion s a nd g a te bu rr s s h a ll not exceed 0.15 mm (0.006 in) per s ide. 3 . dimen s ion e1 doe s not incl u de inter-le a d fl as h or protr us ion s . inter-le a d fl as h a nd protr us ion s s h a ll not exceed 0.25 mm (0.010 in) per s ide. 4. dimen s ion b doe s not incl u de d a m ba r protr us ion. allow ab le d a m ba r protr us ion s h a ll b e 0.0 8 mm tot a l in exce ss of the b dimen s ion a t m a xim u m m a teri a l condition. d a m ba r c a nnot b e loc a ted on the lower r a di us of the foot. minim u m s p a ce b etween protr us ion a nd a dj a cent le a d i s 0.07 mm. 5. dimen s ion d a nd e1 to b e determined a t d a t u m pl a ne h. 8 a2 b s ide view end view top view a2 a l l1 d 1 2 3 e1 n b pin 1 indic a tor thi s corner e e
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